Submitted by james on Tue, 09/26/2017 - 11:44

DE0: Altera Cyclone V SoC (FPGA with dual-core Cortex™-A9) in the DE0-SoC Development Kit. I paid $103.75. The “DE0” name has been used for board based on Cyclone III, IV or V SoCs, I used the latest version based on and Cyclone V SoC.


DE0-Nano-SoC Kit/Atlas-SoC Kit

This board boasts a Cyclone V SoC with 49K logical elements plus an integrated dual-core ARM Cortex A9 Processor. The board also has 3.3V Arduino shield compatibility via female headers, 1 Gig of external DDR3 SDRAM, and support for gigabit ethernet.

The key links here are for ordering (google for it, or follow the first link below), downloading the “DE0-Nano-SoC CD-ROM” (use the “Manual/DE0-Nano-SoC_Getting_Started_Guide.pdf”) and following the “OpenCL Mandelbrot Demo on Atlas-SoC.”  I included other links for completeness, but they were not directly important to doing what I do in this article. The getting started guide from the downloaded “CD” (downloads as a ZIP file) has step-by-step instruction beginning with installing Quartus II and SoC Embedded Design Software (EDS) but Intel’s website has changed so the step-by-step is out-of-date.  I have noted the links that I used to download “Quartus Prime software Lite edition” (supports the Cyclone V SoC on the board, and includes the Nios II EDS). The software for this board is free, whereas the cost for software to support Intel’s more powerful FPGAs range from $2,995 to $4,995 per seat. Amusingly, the getting started guide makes references to hardware features (like “LED9”) without identifying them in the getting started guide. Strictly speaking, understanding them is not required to get through the Getting Started Guide. There are clearly labelled diagrams of the parts, including reset switches and LEDs, in the DE0-Nano-SoC User Manual (DE0-Nano-SoC_User_manual.pdf) which is available from the downloads on terasic’s website (the first link below). To their credit, the JTAG device showed up automatically in Windows 10 – it did not require the manual setup that the Getting Started Guide shows how to do. All in all, the installation of software and getting it to work was quite easy thanks to the Getting Started Guide.

Hot tips: The DIP switch settings in the Getting Started Guide are what we need but were not the default settings on the board as the manual said. I had to change them to match the guide, and that was necessary to get the programming to work.  Otherwise, following the Getting Started Guide through Section 4 is absolutely the document to follow in order to be setup up and ready to run any of my example programs. You can skip Section 5 (using the ARM processor) of the Getting Started Guide since I am focusing on programming the FPGA. That said, you might notice that the Getting Started Guide only loaded a precompiled example program into the FPGA without even hinting at how to build the FPGA code. You won’t find a Makefile, a Project File or any other familiar software project description file in the “my_first_fpga” example. After all, a hardware engineer would know about synthesis tools just like a software engineer would know about compilers. HOW TO BUILD

I did my work for this board from Windows. I downloaded and installed the software from a file called “Quartus-lite-” (yes, a “tar” for Windows not a “zip”… suggesting that the creators spend more time in Linux than Windows). The QPF (Quartus Project File) is the file to open with “Open Project” under Quartus.

OpenCL Tbird for DE0-Nano-SoC

Submitted by reinders on Mon, 10/02/2017 - 01:15

I was able to figure out how to use OpenCL on the DE0 through a combination of Intel FPGA SDK for OpenCL - Intel Cyclone V SoC Getting Started Guide and a "BSP" (Board Support Package), for the DE0, found thanks to a key forum post.

The Intel documentation hints that OpenCL programming can consume a lot of FPGA logic by including this  cautionary message: "The Cyclone V SoC FPGA... is not considered a large FPGA. However, if you structure your kernel code in a way that optimizes hardware usage, it can provide sufficient hardware resources to implement complex computations. Intel recommends that you consult the Intel FPGA SDK for OpenCL Best Practices Guide to obtain a good understanding of the Intel FPGA SDK for OpenCL Offline Compiler, and for strategies on area optimization."


OpenCL: OpenCL Mandelbrot Demo on Atlas-SoC

T-bird Signal on DE0

Submitted by james on Fri, 09/29/2017 - 20:53






module counter32 ( CLOCK_50, counter_out ); 
input   CLOCK_50;                       
output [31:0] counter_out;
reg    [31:0] counter_out;
always @ (posedge CLOCK_50)
		counter_out <= #1 counter_out + 1;


module lightsequencer( enable, in3, out3 );
input enable;
input [2:0] in3;
output [2:0] out3;
assign out3[2] = in3[2]    && !enable;
assign out3[1] = &in3[2:1] && !enable;
assign out3[0] = &in3[2:0] && !enable;